Business and consumers use a wide array of wireless devices, including cell phones, wireless local area network (LAN) cards, global positioning system (GPS) devices, electronic organizers equipped with wireless modems, and the like. The increased demand for wireless communication, and other mobile, devices has created a corresponding demand for technical improvements to such devices. Generally speaking, more and more of the components of conventional radio receivers and transmitters are being fabricated in a single integrated circuit package.
One important aspect of wireless communication devices having integrated circuits is battery life. In order to maximize battery life for these wireless communication devices, much emphasis has been placed on minimizing power consumption in the integrated circuits of the wireless communication devices.
Conventional approaches to minimizing power consumption in integrated circuits include voltage scaling. Voltage scaling is useful for minimizing dynamic power consumption due to switching. However, voltage scaling does not provide much, if any, benefit for static power consumption due to leakage current. This causes problems in digital technologies that have been scaled to be smaller and smaller, resulting in more leaky circuits. In fact, the leakage current, which used to be a relatively small component of total power consumption, is actually dominating total power consumption for many deep submicron digital chips. A digital chip with several million transistors, for example, may have a DC leakage current of several milliamps, or even tens of milliamps, when the chip is in a standby mode. In typical mobile devices, this amount of leakage current, and its corresponding power consumption, is unacceptable.
Conventional approaches to minimizing power consumption in integrated circuits also include threshold scaling. Threshold scaling is useful for minimizing static power consumption due to leakage current. However, threshold scaling does not provide much, if any, benefit for dynamic power consumption due to switching.
Thus, in order to make use of both voltage scaling to minimize dynamic power consumption and threshold scaling to minimize static power consumption, one approach has been to incorporate switching software into the chip. This switching software determines the voltage and threshold needed to operate a particular task and switches the chip into a corresponding mode while that task is being performed. One drawback to this approach includes the use of a safety margin in the calculation of critical path delays when selecting the mode, which results in the chip possibly not operating at its optimum potential.
A recent solution to this problem involves using adaptive voltage scaling and adaptive threshold scaling cooperatively based on a clock frequency for the chip as measured on the chip. This allows adaptive voltage scaling to be used to minimize dynamic power consumption at higher frequencies and adaptive threshold scaling to be used to minimize static power consumption at lower frequencies, without the use of an arbitrary safety margin for critical path delays. This solution involves the use of a delay line that mirrors a critical path for the application. However, using this approach, the critical path delay has to be matched to the length of the delay line at design time. In addition, the desired length of the delay line may vary based on a range of supply voltages and clock frequencies.